1. Field of the Invention
The invention relates generally to tri-state circuit and more particularly to an integrated high-speed tri-state circuit having low power consumption.
2. Related Art
FIG. 1 shows an integrated circuit with a conventional pull-up type tri-state circuit. In the figure, an input of an inverter 13 is connected to a data line 11 and its output is connected to one input of an OR gate 15 as well as one input of an AND gate 16. An input of an inverter 14 is connected to an enable (EN) line 12 as well as the other input of the OR gate 15 and its output is connected to the other input of the AND gate 16. The gate of a P-channel enhancement-type MOSFET (hereafter, called P-type FET) 17 is connected to an output of the OR gate 15. A drain terminal of the P-type FET 17 is connected so that a first source voltage Vc is applied, and its source terminal is connected to a drain terminal of a N-channel enhancement-type MOSFET (hereafter, called N-type FET) 18. A gate terminal of the N-type FET 18 is connected to an output of the AND gate 16 and its source terminal is connected to a second source voltage or reference potential (ground potential). A point of connection of the source terminal of the P-type FET 17 with the drain terminal of the N-type FET 18 is connected to an output line 10. One end of a pull-up resistance 19 is connected to the first source voltage Vc and the other end of the resistance 19 is connected to the output line 10. The output line 10 is connected to an input circuit 21 to a next-stage CMOS circuit. In the CMOS circuit, the input to the next-stage CMOS circuit becomes unsteady if the output line 10 is in a floating state. This is the reason the pull-up resistance 19 is provided.
The operation of the circuit illustrated in FIG. 1 will now be described. If an EN signal at a logic level 1 (or high logic signal) is provided to the enable line 12, an output signal from the OR gate 15 always becomes a logic level 1 and thus the MOSFET 17 is always rendered non-conductive. On the other hand, an output signal from the AND gate 16 is always at the logic level 0 (or low logic level signal) and thus the MOSFET 18 is always rendered non-conductive. From the above, when an EN signal is at the logic level 1, both FET 17 and FET 18 are always non-conductive, regardless of the value of a data signal provided to the data line 1. That is, when an EN signal is at the logic level 1, the output line 10 is put in a high impedance state.
When an EN signal at the logic level 0 is supplied to the enable line 12, a logic level 1 signal on data line 11 causes an output signal from the OR gate 15 to assume the logic level 0 and an output signal from the AND gate 16 to assume the logic level 0. Accordingly, the P-type FET 17 rendered conductive and, on the other hand, the N-type FET 18 is rendered non-conductive. Thus, this causes the output signal on line 10, to become the logic level 1.
If an EN signal at the logic level 0 is supplied to the enable line 12, a logic level 0 signal on data line 11 causes an output signal from the OR gate 15 to assume the logic level 1 and an output signal from the AND gate 16 to assume the logic level 1. Accordingly, the P-type FET 17 is rendered non-conductive and, on the other hand, the N-type FET 18 is rendered conductive. Thus, this causes the output signal on line 10 to become the logic level 0.
As is obvious from the above, this known integrated circuit takes three states (1 level state, 0 level state, and high impedance state) in response to the enable signal.
In the above conventional integrated circuit, when a data signal at the logic level 0 is supplied to the data line 11, an output signal at the logic level 0 is provided to the output line 10. In a state where a data signal at the logic level 0 has been given to the data line 11, if an EN signal applied to the enable line 2 changes from the logic level 0 to the logic level 1, the output circuit assumes a high-impedance state. Accordingly, floating capacitance in the output line 10 gradually charges up, through the pull-up resistance 19, to the source voltage level Vc. In such a state, the output signal rises, for example, in 500-600 ns to 5-6 .mu.s in accordance with the time constant determined by the pull-up resistance 19 and the above floating capacity, to the source voltage level Vc from the level 0. Since the output signal does not rise abruptly in such a state, during this transient period, a through current continues to flow in the next-stage CMOS circuit and thereby power is consumed. Furthermore if the data signal on line 11 involves many logic level 0 signals, the above-described problem is exascerbated.
The present invention is intended to solve such a problem, in particular, to provide a high-speed tri-state integrated circuit of low power consumption.